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dma 2271, dma 2280, dma 2281 c/d/d2Cmac decoder edition august 5, 1991 6251C331C1e micronas intermetall micronas
dma 2271, dma 2280, dma 2281 2 contents page section title 3 1. introduction 3 1.1. general information 3 1.2. environment 5 2. specifications 5 2.1. outline dimensions 5 2.2. pin connections 6 2.3. pin descriptions 8 2.4. pin circuits 9 2.5. electrical characteristics 9 2.5.1. absolute maximum ratings 9 2.5.2. recommended operating conditions 11 2.5.3. recommended crystal characteristics 12 2.5.4. characteristics 15 2.5.5. dram interface characteristics 17 2.5.6. waveforms 20 2.5.7. frequency responses 21 3. functional description 21 3.1. clock and data recovery 21 3.1.1. the code converter 21 3.1.2. the video clamping circuit and the agc circuit 21 3.1.3. the phase comparator and the pll filter 21 3.1.4. the data slicer and the synchronization circuit 21 3.2. video processing 21 3.2.1. the luminance store 22 3.2.2. the luminance interpolating filter 22 3.2.3. the contrast multiplier 22 3.2.4. the chrominance store 22 3.2.5. the line interpolating filter 22 3.2.6. the chrominance interpolating filter 22 3.2.7. the color saturation multiplier 22 3.2.8. the color multiplier 22 3.3. sound/data processing 23 3.3.1. the golay and pt byte decoder 23 3.3.2. the address comparator 23 3.3.3. the sound decoder 23 3.3.4. the sound multiplex 24 3.3.5. the f a audio clock 24 3.3.6. the buffer for packet 0 25 4. the three serial interfaces 25 4.1. the s bus interface and the s bus 25 4.2. the im bus interface and the im bus 25 4.2.1. the im bus 25 4.2.2. im bus addresses and instructions 25 4.3. the burst bus 26 4.3.1. control and status registers
dm a 2271, dm a 2280, dm a 2281 3 the dma 2271, dma 2280, and dma 2281 c/d/ d2mac decoders 1. introduction 1.1. general information digital realtime signal processor for processing c/d/ d2mac video, sound, and data signals digitized by the vcu 2133 v ideo codec in digital ctv receivers accord- ing to i ntermetall's digit 2000 system of or in ana - log ctv re ceivers or in standalone c/d/d2mac de - coders (see figs. 11 to 13). in order to receive tv channels transmitted via satellite or cable network using the newly established c/d/ d2mac standards instead of p al or secam, decod- ers are required for decoding the tv video and sound signals. the dma 2271, dma 2280, and dma 2281 are suitable for this purpose, in conjunction with the digit 2000 digital tv system and also for standalone solu- tions. the dma 2271 is only able to decod e d2mac/packet signals, in contrast to the dma 2280 which decodes d mac/packet signals and the dma 2281 which decodes d2, d or cmac/packet signals. the dma 2271, dma 2280, and dma 2281 are a pro- grammable circuits, produced in cmos technology and housed in a 68pin plcc package. these decoders contain on a single silicon chip the following functions (see fig. 14): code converter circuitry for clamping, agc and pll chroma and luma store for expansion of the mac sig- nal chroma and luma interpolating filter contrast multiplier with limiter for the luminance signal color saturation multiplier with multiplexer duobinary decoder (data slicer) synchronization descrambler and deinterleaver packet linker packet 0 bu f fer sound decoder and sound multiplexer im bus interface circuit for communicating with the ccu 1.2. environment fig. 11 shows the block diagram of a digital ctv receiv- er system digit 2000, equipped with c/d/d2mac and t eletext, and suited for the p al and secam standards. standalone c/d/d2mac decoders are shown in figs. 12 and 13. these two versions can either be inte- grated into analog ctv receivers, or can serve as standalone c/d/d2mac decoders. ccu 3000 nvm 3060 1/2 vcu 2136 mcu 2600 dpu 2553 tpu 2735 dram spu 2243 pvpu 2204 dma 2281 1/2 vcu 2136 amu 2481 acp 2371 v ideo dram r g b defl. s1 s2 s3 sound s4 fig. 11: block diagram for a multistandard ctv re- ceiver according to the digit 2000 system and equipped with d2mac ccu 3000 vcu 2133 a/d part mcu 2600 tpu 273 5 dram dma 2281 vcu 2133 d/a part amu 2481 v ideo dram r g b defl. s1 s2 s3 s4 fig. 12: block diagram for a standalone c/d/ d2mac decode r , equipped with the vcu 2133 v ideo codec for a/d and d/a conversion (reduced chroma bandwidth)
dma 2271, dma 2280, dma 2281 4 ccu 3000 1/2 uvc 3130 mcu 2600 tpu 2735 dram dma 2281 switch amu 2481 video dram r g b s1 s2 s3 s4 fig. 13: block diagram for a standalone c/d/ d2mac decoder, equipped with the uvc 3130 for a/d and hdaa or d/a conversion (full chroma band- width) hdaa r g b gray converter clamping agc phase com- parator, pll filter data slicers, synchro- nization imbus interface luma store chroma store des- crambler, deinter- leaver golay, pt byte and tg decoder address com- parator luma inter- polating filter line inter- polating filter contrast multiplier chroma interpo- lating filter packet linker error correction, expansion, error concealment memory control sound multiplex audio clock generator buffer for packet 0 color multiplexer color saturation multiplier t0 dma 2271, dma 2280, dma 2281 88 odi 3946 48 49 25 26 4 5053 57 58 60 69 54 12 13 14 62 15 61 63 f m reset v sup 55 56 16 17 65 67 66 64 1 7 68 8 26 91 1 3138 18 2124, 2730 8 fig. 14: block diagram of the dma 2271, dma 2280, dma 2281 c/d/d2mac decoders
dma 2271, dma 2280, dma 2281 5 2. specifications 2.1. outline dimensions fig. 21: dma 2271, dma 2280, dma 2281 in 68pin plcc package weight approx. 4.5 g, dimensions in mm 2.2. pin connections pin nr. signal name symbol 1 ram data input/output rdat 2 ram address output 0 (lsb) ra0 3 ram address output 1 ra1 4 ram address output 2 ra2 5 ram address output 3 ra3 6 ram address output 4 ra4 7 ram read/write output r/wq 8 row address select output rasq 9 ram address output 5 ra5 10 ram address output 6 ra6 11 ram address output 7 (msb) ra7 12 im bus clock input imc 13 im bus ident input imi 14 im bus data input/output imd 15 reset input resq 16 18.432 mhz output xtal1 17 18.432 mhz input xtal2 18 output disable input odi 19 leave vacant 20 leave vacant 21 chroma output 7 (msb) co7 22 chroma output 6 co6 23 chroma output 5 co5 24 chroma output 4 co4 25 pll tuning data output plld 26 pll tuning clock output pllc 27 chroma output 3 co3 28 chroma output 2 co2 29 chroma output 1 co1 30 chroma output 0 (lsb) co0 31 luma output 0 lo0 32 luma output 1 lo1 33 luma output 2 lo2 34 luma output 3 lo3 35 luma output 4 lo4 36 luma output 5 lo5 37 luma output 6 lo6 38 luma output 7 (msb) lo7 39 baseband input 7 (msb) bi7 40 baseband input 6 bi6 41 baseband input 5 bi5 42 baseband input 4 bi4 43 baseband input 3 bi3 44 baseband input 2 bi2 45 baseband input 1 bi1 46 baseband input 0 (lsb) bi0 47 leave vacant 48 clamping output clmp 49 agc output agc 50 combined output for horizon- tal blanking and key key
dma 2271, dma 2280, dma 2281 6 51 combined output for horizon- tal and vertical blanking cbl 52 data burst window output dbw 53 composite sync output csync 54 test input/output t0 55 packet data output pdat 56 descrambled packet data in- put dpdat 57 teletext sync output tsync 58 burst sync output bsync 59 burst data input/output bdat 60 burst clock output bclk 61 ground gnd 62 main clock input mclk 63 supply voltage v sup 64 sound bus ident output sbi 65 audio clock output aclk 66 sound bus data output sbd 67 sound bus clock output sbc 68 column address select out- put casq 2.3. pin descriptions pin 1 ram data input/output rdat (fig. 27) serves as an output for writing data into the external ram and as an input for reading data from the external ram. pins 2 to 6 and 9 to 11 ram address outputs ra0 to ra7 (fig. 210) these pins are used for addressing the external ram. pin 7 ram read/write output r/wq (fig. 210) by means of this output the external ram is switched to read or write mode. pin 8 row address select output rasq (fig. 210) this pin supplies the row address select signal to the external ram. pins 12 to 14 im bus connection imc, imi,imd (figs. 22 and 26) these pins connect the dma 2271, dma 2280 and dma 2281 to the im bus. via the im bus the dma 2271, dma 2280 and dma 2281 communicate with the ccu 3000 central control unit. the data transferred via the im bus are listed in tables 41 to 44. pin 15 reset input resq (fig. 25) pin 15 is used for hardware reset. reset is actuated at low level, at high level the dma 2271, dma 2280, and dma 2281 are ready for operation. pins 16 and 17 xtal 1 output and xtal 2 input (fig. 211) these oscillator pins are used to connect an 18.432 mhz crystal, which determines the aclk audio clock signal supplied by pin 65. alternatively, an 18.432 mhz clock may be fed to pin 17. pin 18 output disable input odi this input serves for fast switchover of the luma and chroma outputs (l0 to l7 and c0 to c7) to high imped- ance, which is required if the tv receiver is equipped with pictureinpicture. low means outputs active, high means outputs are disabled. pin 19 leave vacant pin 20 leave vacant pins 21 to 24 and 27 to 30 chroma outputs c7 to c0 (fig. 28) via these pins, the dma 2271, dma 2280, and dma 2281 deliver the digital chrominance signal (ry, by) in multiplexed operation to the vcu 2133 video codec unit, where it is converted to an analog signal. pin 25 pll tuning data output plld (fig. 28) this pin supplies the 12bit data word containing the pll tuning information from the pll filter of the dma 2271, dma 2280, and dma 2281. this information is needed by the voltage controlled oscillator (vco) con- tained on the mcu 2600 clock generator ic and closes the pll which determines the main clock signal. pin 26 pll tuning clock output pllc (fig. 28) this pin supplies the data clock signal needed for the se- rial data transfer of the 12bit pll tuning information. pins 31 to 38 luma outputs l0 to l7 (fig. 28) via these pins, the dma 2271, dma 2280 and dma 2281 deliver the digital luminance signal to the vcu 2133 video codec unit, where it is converted to an ana- log signal. pins 39 to 46 baseband input bi7 to bi0 (fig. 23) via these inputs, the dma 2271, dma 2280, and dma 2281 receive the digitized baseband signal from the vcu 2133 video codec. pin 47 leave vacant pin 48 clamping output clmp (fig. 29) this pin supplies a pdm (pulse density modulated) sig- nal for clamping the analog baseband signal at the input of the analog to digital converter.
dma 2271, dma 2280, dma 2281 7 pin 49 agc output agc (fig. 29) this tristatecontrolled output allows automatic gain control (agc) with a threelevel signal. high level means that the input level of the baseband signal is too low, low level means that the input level of the baseband signal is too high. in the high impedance state the level of the baseband signal is in the proper range. pin 50 combined output for horizontal blanking and color key (fig. 29) this output is a tristatecontrolled output. in conjunction with the input load represented by the vcu 2133 video codec, the three level blanking and key is produced. high level means active line, high impedance state means horizontal blank and low level means color key. pin 51 combined output for horizontal blanking and vertical blanking cbl (fig. 29) in conjunction with the input load represented by the vcu 2133 video codec, the three level combined blank- ing pulse is produced. high level means active line, high impedance means horizontal blanking and low level means vertical blanking. pin 52 data burst window dbw (fig. 29) this output supplies the data burst window signal which can be used to switch an external deemphasis net- work. this signal is active high in line 625 and during the data burst in each line. pin 53 composite sync output csync (fig. 28) this output supplies a composite synchronization signal as it may be used by the dpu 25xx deflection processor or by other units which need a composite synchroniza- tion signal which is not contained in the mac baseband signal. pin 54 test input/output t0 (fig. 28) this pin is used for testing the dma 2271, dma 2280, and dma 2281 during production. pin 55 packet data output pdat (fig. 210) pdat is used to put out each received packet, deinter- leaved, with golay corrected header and with errorcor- rected bt byte. this pin used to connect the dma 2275, dma 2285 or dma 2286 descrambler ic. pin 56 descrambled packet data input dpdat (fig. 22) this pin is used in conjunction with pdat, if conditional access signals must be descrambled, dpdat receives the descrambled packet data from the dma 2275, dma 2285 or dma 2286 descrambler ic. pin 57 teletext sync output tsync (fig. 29) this pin supplies a signal which marks the part of the vbi lines containing teletext data. pin 58 burst sync output bsync (fig. 24) this connection supplies a synchronization signal for the burst data output. the sync pulse marks the line synchronization word lws of each, and the clock run in cri and frame sync word fsw in line 625. pin 59 burst data output bdat (fig. 24) this output supplies the recovered an decoded duobina- ry data contained in a mac signal. this signal may serve as an input signal for the tpu 27xx teletext processor or the dma 2275, dma 2285, dma 2286 mac des- crambler processor or for other purposes. pin 60 burst clock output bclk (fig. 29) this pin supplies the data clock signal required for the serial data transfer of the burst data signal. the fre- quency of this signal is equal mclk or mclk/2 con- trolled by parameter data rate select drs via im bus. pin 61 ground gnd pin 62 main clock input mclk (fig. 24) by means of this input, the dma 2271, dma 2280 and dma 2281 receive the required main clock signal from the mcu 2600 clock generator ic. pin 63 supply v sup pin 64, 66, and 67 sound bus ident sbi (fig. 29) data sbd and clock sbc (fig. 28) these pins supply the clock, data and ident signals to the amu 2481 mixing unit via the serial threeline sound bus. pin 65 audio clock output aclk (fig. no tag) this pin supplies the aclk audio clock signal for the amu 2481. pin 68 column address select casq (fig. 210) this pin supplies the column address select signal for the external ram.
dma 2271, dma 2280, dma 2281 8 2.4. pin circuits the following figures schematically show the circuitry at the various pins. the integrated protection structures are not shown. the letter apo means pchannel, the let- ter ano nchannel. p n v sup gnd fig. 22: input pins 12, 13, 18 and 56 pp nn v sup gnd bias fig. 23: input pins 39 to 46 p n p n gnd v sup fig. 24: input pin 62 n p p p n n v sup gnd fig. 25: input pin 15 p n n v sup fig. 26: input/output pin 14 gnd pp nn v sup gnd fig. 27: input/output pin 1 v sup gnd n fig. 28: output pins 21 to 38, 48, 52 to 54, 66 and 67 p n v sup gnd fig. 29: output pins 48 to 52, 57 to 60 and 64 p n v sup gnd fig. 210: output pins 2 to 11, 55 and 68
dma 2271, dma 2280, dma 2281 9 v sup gnd p n p n f eclk 0.5m 16 17 fig. 211: crystal oscillator pins 16 and 17 n p v sup gnd fig. 212: output pin 65 2.5. electrical characteristics all voltages are referred to ground. 2.5.1. absolute maximum ratings symbol parameter pin no. min. max. unit t a ambient operating temper- ature 0 65 c t s storage temperature 40 +25 c v sup supply voltage 19, 47, 63 6 v v i input voltage, all inputs 0.3 v v sup v o output voltage, all outputs 0.3 v v sup i o output current, all outputs 10 +10 ma 2.5.2. recommended operating conditions at t a = 0 to 65 c, f f m = 20.25 mhz symbol parameter pin no. min. typ. max. unit v sup supply voltage 19, 47, 63 4.75 5.0 5.25 v v f midc f m clock input d.c. voltage 62 1.5 3.5 v v f miac f m clock input a.c. voltage (pp) 0.8 2.5 v t f mih t f mil f m clock input high/low ratio 0.9 1.0 1.1 t f mihl f m clock input high to low transition time 0.15 f f m v reil reset input low voltage 15 0.8 v v reih reset input high voltage 2.4 v t reil reset input low time 2 m s v vil video input low voltage 39 to 46 2.2 v v vih video input high voltage 2.8 v
dma 2271, dma 2280, dma 2281 10 recommended operating conditions, continued symbol parameter pin no. min. typ. max. unit v f vih video input hold time after f m clock input 39 to 46, 62 14 ns v vis f video input setup time be- fore f m clock input 4 ns v odil outputs disable inputs low voltage 18 0.8 v v odih outputs disable inputs high voltage 2.4 v v dsil descrambled data input low voltage 56 0.8 v v dsih descrambled data input high voltage 2.4 v v f al f a clock input low voltage 17 0.8 v v f ah f a clock input high voltage v sup 0.8v t f ah t f al f a clock input high/low ratio 0.9 1.0 1.1 t f ahl f a clock input high to low transition time 0.15 f f a t f alh f a clock input low to high transition time 0.15 f f a f f a f a clock input frequency 18.432 mhz v imil im bus input low voltage 12 to 14 0.8 v v imih im bus input high voltage 2.4 v f f i f i im bus clock frequency 0.05 1000 khz t im1 f i clock input delay time after im bus ident input 0 t im2 f i clock input low pulse time 3.0 m s t im3 f i clock input high pulse time 3.0 m s t im4 f i clock input setup time before ident input high 0 t im5 f i clock input hold time after ident input high 1.5 m s t im6 f i clock input setup time before ident endpulse input 6.0 m s
dma 2271, dma 2280, dma 2281 11 recommended operating conditions, continued symbol parameter pin no. min. typ. max. unit t im7 im bus data input delay time after f i clock input 12 to 14 0 t im8 im bus data input setup time before f i clock input 0 t im9 im bus data input hold time after f i clock input 0 t im10 im bus ident endpulse low time 3.0 m s 2.5.3. recommended crystal characteristics symbol parameter min. typ. max. unit t a ambient operating temperature 20 +85 c f p parallel resonance frequency 18.432*) mhz d f p f p accuracy of adjustment 40 ppm d f p f p frequency deviation versus temperature 40 ppm r r series resistance 50 w c 0 shunt capacitance 5.5 7.5 pf c 1 motional capacitance 15 20 ff p rated drive level 0.02 mw f p f h spurious frequency attenuation 20 db *) at c l = 10 pf. this frequency applies for a certain application. for other applications, an appropriate frequency must be chosen.
dma 2271, dma 2280, dma 2281 12 2.5.4. characteristics at t a = 0 to 65 c, v sup = 4.75 to 5.25 v, f f m = 20.25 mhz symbol parameter pin no. min. typ. max. unit test conditions i sup supply current 63 100 130 ma v f aol f a audio clock output low voltage 65 2.0 v i f ao = 0.5 ma v f aoh f a audio clock output high voltage 3.0 v i f ao = 0.5 m a t f ahl f a audio clock output high to low transition time 10 ns f f a f a audio clock output frequency 18.432 mhz v lcol luma/chroma output low voltage 21 to 24, 27 to 38 0.3 v i lco = 6 ma i lcoh luma/chroma output high current 10 m a v lco = 5 v t lcot luma/chroma output transition time 10 ns t f lcoh luma/chroma output hold time after f m clock input 21 to 24, 27 to 38, 12 ns t f lcos luma/chroma output setup time after f m clock input 62 30 ns t ld luma output delay time after 194 +839 m s v pol pll bus output low voltage 25, 26 0.2 v i po = 2 ma i poh pll bus output high current 10 m a v po = 5 v f f p f p clock frequency 26 f f m 4 t f poh t f pol f p clock output high/low ratio 0.8 1 1.25 t pdos f pll data output setup time before f p clock output 25, 26 20 ns t f pdoh pll data output hold time after f p clock output 80 ns v sol s bus output low voltage 64, 66, 67 0.2 v i so = 2 ma i soh s bus output high current 10 m a v so = 5 v t sot s bus output transition time 10 ns f f s f s s clock output frequency 67 f f a 4 t s2 t s1 f s s clock output high/low ratio 0.9 1 1.1 t s3 f s s clock output setup time before ident endpulse output 64, 67 160 220 ns
dma 2271, dma 2280, dma 2281 13 characteristics, continued symbol parameter pin no. min. typ. max. unit test conditions t s4 s bus data output setup time before f s s clock output 66, 67 100 ns t s5 s bus data output hold time after f s s clock output 100 ns t s6 s bus ident endpulse output low time 64 300 400 ns v bol burst bus output low voltage 58 to 60 0.4 v i dmo = 1.6 ma v boh burst bus output high voltage 2.8 v i dmo = 0.1 ma t bt burst bus output transition time 10 ns f f b f b burst bus clock frequency 60 f f m or 2 f f m t b3 t b2 f b clock output high/low ratio 0.9 1 1.1 t b1 f b clock output delay time after ident output 58, 60 0 t b4 ident output delay time after f b clock 0 t b5 burst bus data output setup time before f d clock output 59, 60 50 ns t b6 burst bus data output hold time after f b clock output 0 v imol im bus data output low voltage 14 0.3 v i imo = 6 ma i imoh im bus data output high current 10 m a v imo = 5 v t 4 im bus data output setup time before f i clock input high 14, 12 0 t 5 im bus data output hold time after f i clock input fall 0 v clol clamping output low voltage 48 0.2 v i clo = 2 ma v cloh clamping output high voltage v sup 0.5 v i clo = 1 ma v agcol agc output low voltage 49 0.4 v i agco = 6 ma i agcoz agc output highimpedance current 10 +10 m a v agc = 0 to 5 v v agcoh agc output high voltage v sup 0.5 v i agc = 1 ma t agco agc output pulse duration 40 ms t sagco agc output pulse start time line no. 624 v hbckol combined horizontal blanking & color key output low voltage 50 0.4 v i hbcko = 6 ma i hbckoz combined horizontal blanking and color key output highim- pedance current 10 +10 m a v hbcko = 0 to 5 v
dma 2271, dma 2280, dma 2281 14 characteristics, continued symbol parameter pin no. min. typ. max. unit test conditions v hbckoh combined horizontal blanking & color key output high voltage 50 4.0 v i hbcko = 0.1 ma t hb2 horizontal blanking output time 10.5 0 m s t ck2 color key high z output low time 2.27 m s t ck1 color key output delay time after horizontal blanking output 5.5 m s t hb1 horizontal blanking output lead time before chroma output high 50, 21 to 24, 27 to 30 5.8 18.4 m s v hvbol combined horizontal and verti- cal blanking output low voltage 51 0.4 v i hvbo = 6 ma i hvboz combined horizontal and vertical blanking output highimpedance current 10 +10 m a v hvbo = 0 to 5 v v hvboh combined horizontal & vertical blanking output high voltage 4.0 v i hvbo = 0.1 ma t vb1 vertical blanking output time 0.64 ms t hb2 horizontal blanking output time 10.5 m s v hbol horizontal blanking output low voltage 52 0.4 v i hbo = 1.6 ma v hboh horizontal blanking output high voltage 2.4 v i hbo = 0.1 ma t hb2 horizontal blanking output low time 12 m s v csol composite sync output low voltage 53 0.4 v i cso = 1.6 ma v csoh composite sync output high voltage 2.8 v i cso = 0.1 ma t cs2 composite sync output low time 1 4.8 m s t cs3 composite sync output low time 2 2.4 m s t vb2 composite sync output delay time after vertical blanking output 51, 53 1.5 m s t csolc composite sync output lead time before chroma output 53, 21 to 24, 27 to 30 4.2 16.8 m s v pdol packet data output low voltage 55 0.4 v i pdo = 1.6 ma v pdoh packet data output high voltage 2.4 v i pdo = 0.1 ma v tsol teletext sync output low voltage 57 0.4 v i tso = 1.6 ma v tsoh teletext sync output high voltage 2.4 v i tso = 0.1 ma
dma 2271, dma 2280, dma 2281 15 2.5.5. dram interface characteristics symbol parameter pin no. min. typ. max. unit test conditions v dil ram data input low voltage 1 0.8 v v dih ram data high voltage 2.0 v t dis ram data input setup time before cas output high 1, 68 75 ns t dih ram data input hold time after cas output high 0 33 ns v dol ram data output low voltage 1 0.4 v i do = 1.6 ma v doh ram data output high voltage 2.4 v i do = 0.1 ma t dt ram data op. transition time 3 50 ns t dhr ram data hold time after ras low 1, 8, 68 140 ns t ds ram data setup time before cas low 20 ns t dh ram data output hold time after cas output low 1, 68 80 ns v aol ram address output low voltage 2 to 6, 9 to 11 0.4 v i ao = 1.6 ma v aoh ram address output high voltage 2.4 v i ao = 0.1 ma t at ram address output transition time 3 50 ns t rah row address output hold time after ras output low 2 to 6, 9 to 11, 8 22 ns t asr row address output setup time before ras output low 30 ns t ar column address output hold time after ras output low 2 to 6, 9 to 11, 68 125 ns t cah column address output hold time after cas output 70 ns t asc column address output setup time before cas output 10 ns v rasol ras output low voltage 8 0.4 v i raso = 1.6 ma v rasoh ras output high voltage 2.4 v i raso = 0.1 ma t rast ras output transition time 3 50 ns t ras ras low pulsewidth 125 3000 ns t rp ras output precharge time 130 ns t rsh ras output hold time after cas output low 8, 68 110 ns v casol cas output low voltage 68 0.4 v i caso = 1.6 ma v casoh cas output high voltage 2.4 v i caso = 0.1 ma t pc page mode cycle time 170 ns
dma 2271, dma 2280, dma 2281 16 dram interface characteristics, continued symbol parameter pin no. min. typ. max. unit test conditions t cast cas output transition time 68 3 50 ns t cp cas output precharge time 70 ns t cas cas low pulsewidth 95 150 ns t rcd cas output delay time after ras output 68, 8 45 ns t csh cas output hold time after ras output 170 ns t crp cas output precharge time before ras output 150 ns v wol write output low voltage 7 0.4 v i wo = 1.6 ma v woh write output high voltage 2.4 v i wo = 0.1 ma t wt write output transition time 3 50 ns t cwl write low before cas high 7, 68 180 ns t wch write command hold time after cas low 80 ns t rch read command hold time after cas high 50 ns t rrh read command hold time after ras high 7, 8 20 ns
dma 2271, dma 2280, dma 2281 17 h l h l h l ident clock data 12 34 678910111213 16 or 24 lsb address msb lsb data msb ab c section a section b section c h l data h l clock h l ident address lsb address msb data msb 5 t im1 t im3 t im2 t im7 t im8 t im9 t im4 t im5 t im6 t im10 fig. 213: im bus waveforms 2.5.6. waveforms h l h l h l sident sclock sdata 16 bit sound 1 a section a section b h l sdata h l sclock h l sident lsb of sound 1 msb of sound 4 16 bit sound 2 16 bit sound 3 16 bit sound 4 64 clock cycles b t s1 t s2 t s4 t s5 t s3 t s6 fig. 214: s bus waveforms
dma 2271, dma 2280, dma 2281 18 h l h l h l sync clock data 644 2 6 7 10 ab section a sections b and c h l data h l clock h l sync t b1 t b3 t b2 t b5 t b6 t b4 fig. 215: burst bus waveforms 645 646 647 648 1 4 5 8 9 11 3 99 100 101 102 103 104 105 c line 1624 line 625 t cwl t ar t csh t pc t ras t wch t rrh t rp t rch t crp t cp t cas t rcd t asr t rah t asc t cah t ds t dh t dhr t dis t dih t rsh row addr. column addr. 0 column address 1 column address 14 row addr. valid data valid data valid data valid data valid data valid data v oh v ol we v oh v ol ras v oh v ol cas v oh v ol dram addr. v oh v ol dout v oh v ol din fig. 216: dram waveform
dma 2271, dma 2280, dma 2281 19 t vb1 first frame composite synchronization pin 53 vertical blanking internal horizontal blanking pin 52 combined horizontal and vertical blanking pin 51 fig. 218a t vb1 second frame composite synchronization pin 53 vertical blanking internal horizontal blanking pin 52 combined horizontal and vertical blanking pin 51 fig. 218b fig. 217: synchronization signals 32 m s t c52 t c53 t vb2 composite synchronization pin 53 vertical blanking internal a 64 m s t c52 t c53 t vb2 composite synchronization pin 53 vertical blanking internal b fig. 218: details of fig. 217
dma 2271, dma 2280, dma 2281 20 chroma out pins 2124, 2730 luma out pins 3138 composite synchronization out pin 53 horizontal blank out pin 52 color key internal combined horizontal blanking and color key pin 50 fig. 219: timing of video and sync signals t ck1 t c52 t ld t c51 t hb1 t hb2 t ck2 2.5.7. frequency responses 5 0 5 10 15 20 25 30 35 40 012345678 fig. 220: luminance channel frequency response db f (mhz) 5 0 5 10 15 20 25 30 35 40 01234 fig. 221: chrominance channel frequency response db f (mhz) i ii iii vi v iv vii viii i ii iii iv vi table 21: selection of the luma filter response lfi curve no. 0 1 2 3 i ii iii iv table 22: selection of the chroma filter response cfi curve no. 0 1 2 3 4 5 6 7 i ii iii iv v vi vii viii
dm a 2271, dm a 2280, dm a 2281 21 3. functional description the dma 2271, dma 2280 and dma 2281 process the digitized d2mac video signal supplied by the vcu 2133 or by the uvc 3130 in the various circuit parts shown in fig. 14. the resulting digital luminance and chrominance signals are then reconverted to analog sig- nals in the vcu or hdaa. the resulting digital audio sig- nals are processed in the amu 2481 audio mixer which provides filtering of the mediumquality channels and al- lows mixing of the four sound channels. the amu ' s digi- tal output signals are reconverted to analog in the acp 2371 audio processo r , which additionally carries out functions like adjustment of volume, bass and treble, loudness, etc. remaining digital data as service and channel information in packet 0 or line 625 can be han- dled by software via the im bus or by additional hardware which uses the serial bdata interface (bdata, b clock and bsync). section 1.2. shows how the dma 2271, dma 2280 and dma 2281 can be used together with other circuits of i nte r met all s ' s digit 2000 di - gi tal tv system to realize a multistandard ntsc/pal/secam/c/ d/d2mac color tv receive r . t o understand the signal processing in the dma 2271, dma 2280, and dma 2281 it may be useful to distin- guish three di f ferent function blocks, namely: clock and data recovery v ideo processing sound/data processing 3.1. clock and data recovery 3.1.1. the code converter this circuit converts the digitized c/d/d2mac base- band signal, delivered by the vcu 2133 in a parallel gray code, into a simple binarycoded signal. the func- tion of the circuit is controlled by the ccu 3000 via the im bus (see section 4.2.). 3.1.2. the v ideo clamping circuit and the agc cir- cuit the video clamping circuit measures the dc voltage lev- el of the clamp period and, by means of the pulse density modulated signal from pin 48, sets the dc level of the clamp period to a constant 5.5 v . the white and the black levels in line 624 are measured for automatic gain con- trol (agc pin 49) and the two values are fed to the im bus interface which organizes the data communication with the ccu. agc (pin 49 ) = high if wl bl < 224 ag c (pi n 49 ) = high impedance if 224 wl bl 240 agc (pin 49) = low if wl bl > 240 3.1.3. the phase comparator and the pll filter the phase comparator derives the reference signal from the slopes contained in the data burst of each line. its output signal, an 8bit word which is passed through a digital lowpass filte r , is added to an 8bit word, vcoa, which is provided by the ccu for adjustment of the crys- tal frequenc y . this digital pll signal is output via pins 25 and 26 and routed to the mcu 2600 clock generator ic thus closing the pll, existing between dma 2271, dma 2280, and dma 2281, vcu 2133 v ideo codec and mcu 2600 clock generator ic. in this wa y , the main clock sig- nal fm of the system is in phase with the duobinary coded signal. t o adjust the crystal frequenc y , it is possible to render in- operative the pll by setting pllo bit 4 in address 201 ( t able 41). the vco in the mcu is then freerunning and the center frequency can be aligned by varying the data word vcoa (bits 0 to 7) in the im bus address 14. 3.1.4 . the data slicer and the synchronization cir- cuit the digitized c/d/d2mac baseband signal is filtered by a 5 mhz lowpass filter before being routed to the data slice r . the output of the slicer is connected to pin 59 (b data). in phase with the continuous bit stream of 20.25 or 10.125 mbit/s, a clock signal (bclock), a synchroni- zation signal (bsync) and a signal for t eletext informa- tion (ttsync) are available at pins 60, 58, and 57 (see fig. 215). the vertical synchronization pulse, onchip, is derived from a 64bit correlator which compares the data stream at the output of the slicer with the fixed frame synchroni- zation w ord (fsw). whenever the correlation is equal to or greater than 61 a frame reset pulse is generated. horizontal synchronization is derived by counting. in phase with the video outputs (l0 to l7, c0 to c7), the various synchronization and blanking signals are out- puts at pins 50 to 53 (fig. 217, 218 and 218). 3.2. v ideo processing the dma 2271, dma 2280, and dma 2281 process the c/d/d2ma c baseband signal, digitized by the vcu or uvc at a sample frequency of 20.25 mhz. for time ex- pansion, the video samples of each line are stored in an onchip ram and read to at the lower frequencies of 13.5 mhz for the luminance signal and 6.75 mhz for the color di f ference signals. 3.2.1. the luminance store t ime expansion of the luminance signal is achieved by digitizing the analog signal at a clock frequency of 20.25 mhz, storing the bytes, and reading them at a frequency of 13.5 mhz. for this, a fast ram is provided onchip.
dma 2271, dma 2280, dma 2281 22 3.2.2. the luminance interpolating filter an interpolation from 13.5 mhz to 20.25 mhz is per- formed in order to overcome the need for a second sys- tem clock of 13.5 mhz and to simplify the reconstruction filters placed after the d/a conversion (rgb outputs of the vcu). the interpolation filter has a linear phase and can be switched to broad or narrow bandwidth by means of the ccu via the im bus (bits 10 and 11, address 201). the different frequency responses are shown in fig. 220 and in table 21. 3.2.3. the contrast multiplier after the luminance interpolating filter is a contrast multi- plier. the contrast setting is controlled by the ccu via the im bus (bits 10 to 15, address 200), depending on the user's instruction. from the contrast multiplier, the digi- tal luminance signal is fed back to the vcu 2133 in the form of an 8bit signal. in the vcu, this signal is con- verted from digital to analog and fed to the rgb matrix. the setting range of the contrast multiplier comprises 6 bits (64 steps). if the product at the multiplier's output is higher than the working range, the largest possible num- ber is output. 3.2.4. the chrominance store the chrominance store contains the color information for 3 lines. it is used for time expansion and line interpo- lation. the input frequency is 20.25 mhz, the output fre- quency 6.75 mhz. 3.2.5. the line interpolating filter the color difference signals are transmitted within alter- nate lines as u and v. a a1, 2, 1o postfilter required to interpolate the color difference information is implem- ented. the action of the filter is for even lines: u = u n ,v = v n1 + v n +1 2 and for odd lines: u = u n1 + u n +1 2 , v = v n 3.2.6. the chrominance interpolating filter after the line interpolating filter the 8bit color difference signals u and v are routed to the chroma interpolating filter which has linear phase and can be switched to dif- ferent frequency responses via the im bus (fig. no tag, table 22) using bits 13 to 15 in address 201. this filter is used for conversion of the sample rate from 6.75 mhz up to 10.125 mhz. 3.2.7. the color saturation multiplier the digital color difference signals u and v are routed to a color saturation multiplier, whose setting is also con- trolled by the ccu via the im bus (address 23). the range of the multiplier comprises 6 bits, with each color difference signal being set independently. the pal matrix in the vcu requires a compensation fac- tor of 0.71. this means that the color saturation factor for (b y) is equal to 0.71 the color saturation factor for (r y). both factors are calculated in the ccu. 3.2.8. the color multiplexer the color difference signals are transferred back to the vcu 2133 in multiplex via a 4line bus. demultiplexing takes place in the vcu. the digital signals are then re- converted to analog. subsequently they are dematrixed in the rgb matrix together with the y signal, giving the rgb signals which drive the output amplifiers of the vcu 2133 video codec. the color multiplexer can drive a 4line bus with an ef- fective sample rate of 5.6025 mhz for each color differ- ence signal or an 8line bus with a sample rate of 10.125 mhz. this function is controlled by the im bus (table 41), using bit 6 in address 201. 3.3. sound/data processing this section begins with a descrambler and deinter- leaver. the descrambler uses the same pseudoran- dom binary sequence (prbs) generator as is used for the scrambling process. its clock rate is 10.125 mhz or 20.25 mhz. the deinterleaver corrects the succession of the transmitted packet bits which are interleaved in or- der to minimize the effect of multiple bit errors. table 31: transmission order 1 2 93 94 95 96 187 188 189 190 ... ... ... 281 282 283 284 375 376 377 378 469 470 471 472 ... ... ... 563 564 565 566 657 658 659 660 751 (1)
dma 2271, dma 2280, dma 2281 23 3.3.1. the golay and pt byte decoder the data format has changed now from data burst for- mat (99 bits) to packet format (751 bits). the header of each packet contains defined addresses for the different sound and data services and four bits representing the sound characteristics. the pt byte of each packet dis- tinguishes between sound and data packets. after cor- rection of header and pt byte with the golay and pt byte decoder, this information is used for automatic con- figuration of the dma 2271, dma 2280, and dma 2281. in addition, the golay decoder is used for measuring the bit error rate of the transmission channel. the bits in er- ror in each packet header are accumulated over one frame (82 packets). the sum is stored in im bus register 206 (table 42) and can be read by the ccu which may control different muting functions. 3.3.2. the address comparator the dma 2271, dma 2280, and dma 2281 d2mac decoders are able to treat different sound services auto- matically by decoding the address field of the packet header. the two continuity bits ci1 and ci0 are used to link successive packets of the same service in case of a 120 byte sound coding service. among the different coding characteristics all combina- tions are possible. the user can select up to four sound channels simultaneously by programming the sound services via the im bus (address 203, 194, 195 and 196). these addresses are compared with the address of each transmitted sound packet. at correspondence, this packet is selected and decoded. 3.3.3. the sound decoder the sound decoding section converts all types of se- lected sound packets into a sequence of 14bit sound samples. the mediumquality channels are up sampled to the 32 khz sampling frequency of the high quality channels, i.e. every sample of a mediumquality channel is put out twice, the second time as a zero sam- ple. the second part of the interpolation is performed in the amu 2481 audio mixer where two oversampling fil- ters are provided. the error correction section uses a range check and/or hamming decoder, depending on the sound coding mode. the hamming decoder is able to correct one error per sample and to detect double er- rors. the range check uses the highly protected scale factor bits to check the msbs of each sample. its error correction and detection abilities are shown in table 32. erroneous samples, i.e. samples with uncorrectable er- rors, are concealed by replacement with interpolated ad- jacent samples. the storage capacity for buffering the sound samples during processing and for obtaining a smooth, regular output of sound samples is provided by an external 64k dram. to ensure the continuity of out- put sound samples in case of packet loss or packet gain, the silence information is used and blocks of samples corresponding to asilenceo are repeated or omitted. 3.3.4. the sound multiplex after extension from 14 bits to 16 bits, the sound sam- ples of the four channels are loaded into a 64bit shift register and transferred to the amu 2481 audio mixer via a serial 3lines s bus. fig. 214 shows the s bus tim- ing. table 32: error correction and detection scale factor protec- tion range defective bits error correc- tion error detec- tion linear: 111 1 110 2 x13, x12 1 101 3 x13, x12, x11 2 011 4 x13 x10 1 2 100 5 x13 x9 1 3 010 6 x13 x8 2 3 001 7 x13 x7 2 4 000 8 x13 x6 2 4 companded: 010 6 x9, x8 1 001 7 x9, x8, x7 2 000 7 x9, x8, x7 2
dma 2271, dma 2280, dma 2281 24 3.3.5. the f a audio clock the audio clock f a for the amu 2481 audio mixer and the acp 2371 audio processor is also supplied by the dma 2271, dma 2280 and dma 2281 which generate this 18.432 mhz clock by means of the crystal con- nected to pins 16 and 17 and supply it via pin 65. the fre- quency of 18.432 mhz is an integer multiple of the sound sampling frequency (32 khz). the f a audio clock output pin 65 can be switched over to the normal main clock f m if a standard other than c/ d/d2mac is received. for this, bit acs in address 204 of the im bus is provided (table 41). the clock frequency f s for the serial s bus is also derived from the audio clock f a (pin 65) by dividing by eight (18.432 mhz: 4 = 4.608 mhz) 3.3.6. the buffer for packet 0 one packet address (000h) is reserved for service and network identification data. a 720bit (90 byte) buffer is implemented onchip especially for this, and is con- trolled by the ccu via the im bus (bits 8 and 9, address 204). the following conditions must be met to ensure that a received packet is stored in this buffer: packet address pa = 000h packet type pt = f8h data group type tg = selected type in im bus register 204 packet 0 status p0 = 0 (see im bus registers 204 and 206) the packet 0 buffer can be read sequentially from a 16bit im bus register (address 210, table 42). one complete read cycle takes about 1.5 ms (im bus fre- quency = 1 mhz). it is possible to reset and to clear the buffer via the im bus in order to repeat the lastread cycle or to receive the next zero packet. additionally, the last 16 bits of the zero packet are used for error check- ing. this crc check calculates the 16bit syndrom vec- tor of the packet concerned and stores it in an im bus register. it can then be used by software for error detec- tion.
dma 2271, dma 2280, dma 2281 25 4. the three serial interfaces 4.1. the s bus interface and the s bus the s bus has been designed to connect the digital sound output of the dma 2271, dma 2280, and dma 2281 mac decoders or the msp 2400 nicam demodu- lator/decoder to audioprocessing ics such as the amu 2481 audio mixer or the acp 2371 audio processor etc., and to connect these ics one to the other. the s bus is a unidirectional, digital bus which transmits the sound information in one direction only, so that it is not neces- sary to solve priority problems on the bus. the s bus consists of the three lines: sclock, sident, and sdata. the dma 2271, dma 2280, and dma 2281 or the msp 2400 generates the signals sclock and s ident, which control the data transfer to and between the various processors which follow the dma 2271, dma 2280, and dma 2281 or the msp 2400. for this, the s clock and sident inputs of all processors in the system are connected to the sclock and sident outputs of the dma 2271, dma 2280, and dma 2281 or the msp 2400. sdata output of the dma 2271, dma 2280, and dma 2281 or msp 2400 is connected to the sdata input of the next following amu, the amu's sdata output is connected to the acp's sdata input and so on. the sound information is transmitted in frames of 64 bits, divided into four successive 16bit samples. each sam- ple represents one sound channel. the timing of a com- plete transmission of four samples is shown in fig. 214, the times are specified under arecommended operat- ing conditionso. the transmission starts with the lsb of the first sample. the sclock signal is used to write the data into the receiver's input register. the sident signal marks the end of one frame of 64 bits and is used as latch pulse for the input register. the repetition rate of sident pulses is identical to the sampling rate of the d2mac or nicam sound signal; thus it is possible to transfer four sound channels simultaneously. the s bus interface of the dma 2271, dma 2280, and dma 2281 mainly consists of an output register, 64bit wide. the timing to write bit by bit is supplied by the s clock signal. in the case of an sident pulse, the con- tents of the output register are written to the sdata out- put. 4.2. the im bus interface and the im bus 4.2.1. the im bus the intermetall bus (im bus for short) was de- signed to control the digit 2000 ics by the ccu central control unit. via this bus the ccu can write data to the ics or read data from them. this means the ccu acts as a master, whereas all controlled ics have purely slave status. the im bus consists of three lines for the signals ident (id), clock (cl) and data (d). the clock frequency range is 50 hz to 1 mhz. ident and clock are unidirec- tional from the ccu to the slave ics, data is bidirection- al. bidirectionality is achieved by using opendrain out- puts. the 2.5 ... 1 kohm pullup resistor common to all outputs must be connected externally. the timing of a complete im bus transaction is shown in fig. 52. in the nonoperative state the signals of all three bus lines are high. to start a transaction the ccu sets the id signal to low level, indicating an address transmission, and sets the cl signal to low level, as well as to switch the first bit on the data line. then eight ad- dress bits are transmitted, beginning with the lsb. data takeover in the slave ics occurs at the positive edge of the clock signal. at the end of the address byte the id sig- nal switches to high, initiating the address comparison in the slave circuits. in the addressed slave, the im bus interface switches over to data read or write, because these functions are correlated to the address. also con- trolled by the address the ccu now transmits eight or sixteen clock pulses, and accordingly one or two bytes of data are written into the addressed ic or read out from it, beginning with the lsb. the completion of the bus transaction is signalled by a short low state pulse of the id signal. this initiates the storing of the transferred data. for future software compatibility, the ccu must write a zero into all bits not used at present. reading undefined or unused bits, the ccu must adopt adon'to care behav- ior. 4.2.2. im bus addresses and instructions by means of the im bus, the dma 2271, dma 2280, and dma 2281 communicate with the ccu 3000 central control unit. the dma 2271, dma 2280, and dma 2281 receive the instructions for the useractuated settings such as color saturation, contrast, sound channel select, packet 0 control, etc., and transmits the measured or re- ceived values such as bit error rate, signal level, sound coding mode,packet 0 data, etc. the address numbers and the associated data for this interaction via the im bus are shown in tables 41 to 44. in these tables awo means data written by the ccu into the dma, and aro means data read by the ccu from the dma. 4.3. the burst bus the burst bus serves for transfer of the digitized d2mac baseband signal, after code conversion, low- pass filtering and slicing as described in sections 3.1.1. and 3.1.4., to e.g., the tpu 2735 teletext processor or the dma 2275/dma 2285/dma 2286 mac descram- bler. timing of the b bus is shown in fig. 215 and under recommended operating conditions.
dma 2271, dma 2280, dma 2281 26 4.3.1. control and status registers note: notused bits must be set to zero for control (receive) registers and are don't care for status (transmit) registers. table 41: 16bit dma control registers, instructions from ccu to dma address label bit no. default setting typical value function 14 14 14 vcoa vcos di1 di2 di3 07 810 11 14 15 0 4 0 0 4 0 vco adjustment (range 128...+127) alignment of the 20.25 mhz vco vco select 1 = vco3 selected 2 = vco2 selected 4 = vco1 selected disable pll output (pin 25, 26) if (di1 . or . di2 . or di3) then pll output = high impedance 23 23 sav sau 27 1015 32 32 25 18 saturation v adjust 0: gain = 0 63: gain = 2 saturation u adjust 0: gain = 0 63: gain = 2 200 200 200 ld cts ct 37 8 1015 4 0 32 6 1 16 luma delay adjust (range 0...30) resolution: 20.25 mhz clock luma contrast switch luma contrast adjust 0: gain = 0 63: gain = 1 if cts = 1 63: gain = 2 if cts = 0 201 201 201 201 201 201 201 dsy dcl dlc nin pllo sta cmp 0 1 2 3 4 5 6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 disable sync outputs (pins 5053, 5860) 0 = enabled 1 = high impedance disable clamping output (pin 48) 0 = enabled 1 = high impedance disable luma/chroma output (pin 2124, 2738) 0 = enabled 1 = high impedance non interlace 0 = interlace on 1 = interlace off pll open 0 = pll closed 1 = pll opened stand alone operation 0 = digital insertion 1 = stand alone chroma output multiplex 0 = 4 x 4 multiplex 1 = 2 x 8 multiplex
dma 2271, dma 2280, dma 2281 27 table 41, continued address label bit no. default setting typical value function 201 201 201 201 dgc l525 lf cf 7 8 1011 1315 0 0 0 0 0 0 0 0 disable gray code converter input signal (pin 3945) 0 = gray coded 1 = binary coded 525 lines standard select 0 = 625 lines standard selected 1 = 252 lines standard selected luma filter selection chroma filter selection 202 202 bd sd 17 915 64 64 64 64 horizontal blank delay adjust (pin 5052) resolution: 10.125 mhz clock comp. sync delay adjust (pin 53) resolution: 10.125 mhz clock 203 203 203 203 c1a c1e c1u c1m 09 10 11 1215 0 0 0 0 128 1 0 12 channel 1 packet address channel 1 enable channel 1 mode update channel 1 mode 194 see register 203 channel 2 195 see register 203 channel 3 196 see register 203 channel 4 197 197 197 197 sfs cd aum drs 010 13 14 15 7 0 0 0 7 0 0 1 subframe select sfs = sample number of the first bit in the selected subframe examples: drs = 1, first subframe sfs = 7 drs = 1, second subframe sfs = 106 drs = 0, first subframe sfs = 14 chip definition 0 = dma 2280 1 = dma 2285 auto mode 0 = auto mode off 1 = sound coding in packet header data rate select 0 = 10.125 mbits/s d2mac 1 = 20.25 mbits/s c/dmac 198 198 198 edc clg cs 03 45 1415 0 0 0 0 2 0 energy dispersal compensation (8...+7) clamping loop gain chip select 0 = im bus of dma 2280 active 1 = im bus of dma 2285 active linear/nicam hamming/parity protection high/medium quality stereo/mono
dma 2271, dma 2280, dma 2281 28 table 41, continued address label bit no. default setting typical value function 199 199 199 199 199 199 199 plls enf2 sls pllg fcd bph sll 0 1 23 45 6 7 815 0 0 0 0 0 0 0 0 0 1 2 0 0 40 0 pll select 0 = d/d2 mac pll 1 = cmac pll enable filter 2 0 for c/d mac 1 for d2 mac slicer select 0 for d2mac 1 for dmac 2 for cmac pll gain 0 = maximal gain 3 = minimal gain full channel data 0: dbw is gated (pin 52) 1: dbw is active all the time burst phase 0 = with dma 2285 1 = only dma 2280 slice level (range 128...+127) for d/d2mac for cmac 204 204 204 204 204 204 204 sbe dgt por poc dsb acs acf 03 47 8 9 10 11 12 0 0 0 0 1 0 1 15 0 0 0 0 1 0 s bus enable data group type selection packet 0 reset 1: select first byte in packet 0 buffer (first byte = data group type dgt) packet 0 clear 1: enable packet 0 buffer to store next packet 0 disable s bus outputs (pins 64, 66, 67) 0 = enabled 1 = high impedance audio clock switch (pin 65) 0: audio clock = main clock 1: audio clock = 18.432 mhz audio clock free running 0 = audio clock locked to main clock 1 = audio clock free running channel 1 enable channel 2 enable channel 3 enable channel 4 enable
dma 2271, dma 2280, dma 2281 29 table 41, continued address label bit no. default setting typical value function 205 205 205 205 205 205 205 205 205 205 205 205 205 205 205 205 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 for test only for test only for test only for test only for test only for test only enable pdat input for test only disable error concealment for test only enable bdat input for test only for test only disable luma/chroma interpolation filters for test only for test only
dma 2271, dma 2280, dma 2281 30 table 42: 16bit dma status registers, information from dma to ccu address label bit no. function 206 206 206 206 206 206 206 206 ber ver c1s c2s c3s c4s p0s sync 07 89 10 11 12 13 14 15 bit error rate number of erroneous bits detected by the golay decoder within the 82 packet headers of one frame version 0: c/d/d2mac decoder 1: d2mac decoder 2: dmac decoder 3: c/d2mac decoder status of sound signal selected by c1a 0: sound signal is inactive or interrupted 1: sound signal is present status of sound signal selected by c2a 0: sound signal is inactive or interrupted 1: sound signal is present status of sound signal selected by c3a 0: sound signal is inactive or interrupted 1: sound signal is present status of sound signal selected by c4a 0: sound signal is inactive or interrupted 1: sound signal is present status of packet 0 buffer 0: packet 0 selected by dgt not received 1: packet 0 received status of frame sync word detector 0: frame sync word not detected within 8 frames 1: frame sync word detected 207 207 wl bl 07 815 white level measured in line 624 (typical value = 240) black level measured in line 624 (typical value = 16) 208 208 208 208 c1l c2l c3l c4l 03 47 811 1215 coding law of sound signal selected by c1a coding law of sound signal selected by c2a coding law of sound signal selected by c3a coding law of sound signal selected by c4a l = 0: companded law 1: linear law h = 0: first level protection 1: second level protection hq = 0: medium quality sound 1: high quality sound s = 0: monophonic sound 1: stereophonic sound 209 209 psl psh 07 815 packet 0 syndrom low byte packet 0 syndrom high byte psl + psh = 0: packet 0 received without error psl + psh > 0: packet 0 received with error 210 210 pdl pdh 07 815 packet 0 data low byte packet 0 data high byte
bits must be set to zero for write registers (w) and are don't care for read registers (r) bits not used in dma 2280 registers, but in other devices dma 2271, dma 2280, dma 2281 31 table 43: dma control and status registers, graphical overview addr. bit no. 1514131211109876543210 14 23 200 201 202 203 194 195 196 197 198 199 204 205 vcos vcoa vco adjustment 00 sav saturation v 40 0 ct luma contrast 32 ld cfi chroma filter 0 msb lsb luma delay dgc disable 0 00 gray csp 00 csp sd composite sync. delay 64 0 0 bd blank delay 64 l shqh c1m channel mode c1u mode 0 update c1a channel packet addres 100 c2a channel packet address 100 c3a channel packet address 100 c4a channel packet address 100 sfs subframe select 7 fcd full 0 chanel data clg clamping 2 loop gain no. direct. w w w w w w w w w w w w w w di3 di2 di1 000 00 1 0 sau saturation u 28 00 0 cse 0 cts 06 0 0 0 cmp chroma 0 mult. sta stand 0 alone pllo pll 0 open nin non 0 interl. dlc disable 0 l/c dcl clamp. 0 off dsy disable 0 sync. l525 525 lines lfi luma filter c1e channel 1 enable l shqh c2m channel mode c2u mode 0 update c2e channel 1 enable l shqh c3m channel mode c3u mode 0 update c3e channel 0 enable l shqh c4m channel mode c4u mode 0 update c4e channel 0 enable drs data 1 rate select cd chip 0 defin. aum auto 0 mode 00 cs chip 0 select 00 0000 bph burst 0 phase sll slice level 0 0 0 edc energy dispersal 2 compensation pllg pll 2 gain sls slicer 1 select enf2 enable 0 filters pllt pll 0 test acf audio 0 free acs clock 0 switch dsb disable 0 s_bus p0c p0 0 clear p0r p0 0 reset dgt data group type 0 sbe s_bus enable 3 0 0 0 206 ber bit error rate r 207 wl white level r 208 c4l coding law ch4 r 209 psl packet 0 syndrom low byte r 210 pdl packet 0 data low byte r t15 0 t14 1 t13 0 t12 0 t11 0 t10 0 t9 0 t8 0 t7 0 t6 0 t5 0 t4 0 t3 0 t2 0 t1 0 t0 0 ver version sync p0s c49 c39 c29 c19 status bl black level l shqh l shqh l shqh l shqh c3l coding law ch3 c2l coding law ch2 c1l coding law ch1 psh packet 0 syndrom high byte pdh packet 0 data high byte
dma 2271, dma 2280, dma 2281 32 table 44: vcu control and status registers, graphical overview addr. bit no. 1514131211109876543210 16 17 18 19 27 br brightness 128 dr white drive red 127 cg cutoff voltage green 127 dg cb cutoff voltage blue 127 msb lsb white drive green 0 rgbc ext. rgb contrast 32 no. direct. w w w w w cr cutoff voltage red 127 127 scs secam 1 chroma sync nie noise 0 invert. enable bcr beam current 0 reduction vi2 video 0 input 2 cob code bits 7 yda luma 1 adder bld blank 1 disable ydas luma 0 adder shift dgd double 1 gain disable ben bit 1 enlarg. db white drive blue 127 bits must be set to zero for write registers (w) and are don't care for read registers (r)
dma 2271, dma 2280, dma 2281 33
dma 2271, dma 2280, dma 2281 34
dma 2271, dma 2280, dma 2281 35
dma 2271, dma 2280, dma 2281 micronas intermetall 36 micronas intermetall gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@intermetall.de internet: http://www.intermetall.de printed in germany by simon druck gmbh & co., freiburg (8/91) order no. 6251-331-1e all information and data contained in this data sheet are with- out any commitment, are not to be considered as an offer for conclusion of a contract nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery dates are ex- clusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas intermetall gmbh does not assume responsibility for patent infringements or other rights of third parties which may result from its use. reprinting is generally permitted, indicating the source. how- ever, our prior consent must be obtained in all cases.

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